The present invention relates to an insulated gate transistor, the channel length of which is minimized to provide high density packaging and to improved the speed and the power-delay performance. Further, the invention relates to various circuits and circuit structures employing such transistors.
Much effort has been made to shorten the channel length of field effect transistors (hereinafter, MOSFETs) to make it possible to increase the number of MOSFETs that can be fabricated on one chip. When the channel length of a MOSFET is shortened, other parameters of the device must be appropriately scaled. A detailed description of such scaling is given in Japanese Patent Application No. 113,709/82. As explained therein, shortening the channel length is necessarily accompanied by an increase in the concentration of impurities in the channel and hence a corresponding decrease in the mobility of carriers in the channel. The effective carrier mobility in the channel is further reduced because the carriers induced beneath the gate insulating layer are distributed to a depth of only about 100 .ANG. or less. This reduced carrier mobility results in a smaller transconductance. As a further difficulty, the input capacitance of the gate is increased when the channel length is shortened. Moreover, the reduction in the channel length is not accompanied by a commensurate improvement in the transistor performance. Another problem is a lowered drain breakdown voltage.
The inventors have conducted various studies to develop an insulated gate electrostatic induction transistor (hereinafter, MOSSIT) free from the above-described difficulties. An improved MOSSIT resulting from these studies is described in Japanese Patent Applications Nos. 108,377/79, 115,491/79 and 113,709/82. Each of the MOSSITs proposed in these applications provides the following four advantages:
(1) the concentration of impurities in the channel is low enough to enable the induced carriers to penetrate deeply into the channel;
(2) the transistor has a high carrier mobility in the channel, thereby providing a greater transconductance;
(3) the transistor has a smaller gate input capacitance so that shortening the channel length is accompanied by a corresponding increase in the operating speed of the transistor; and
(4) the transistor consumes less power and has an increased drain breakdown voltage.
The present invention is a further improvement on these MOSSITs. It is a primary object of the invention to provide an integrated semiconductor circuit using an insulated gate electrostatic induction transistor that has a greatly shortened channel.